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the pfe1500 is a 1500 w ac to dc power - fac to r - corrected (pfc) power supply that convert s standard ac or hvdc power into a main output of 12 vdc for powering intermediate bus architectures (iba) in high performance and reliability servers, routers, and netw ork switches. the pfe1500 s eries meet s international safety standards and displays the ce - mark for the european low voltage directive (lvd). ? high efficiency, typ. 94% efficiency at half load ? universal input voltage range: 90 - 264 v ac ? high voltage dc input: 180 - 350 vdc (option for 400 vdc) ? ac input with power factor correction ? always - on standby output (model dependent) : o programmable 3.3 v / 5 v (16.5 w) o 12 v @ 3 a (36 w) ? hot - plug capable ? parallel operation with active digital curr ent sharing ? digital controls for improved performance ? high density design: 35 w/in 3 ? small form factor: 54.5(w) x 40.0(h) x 321.5(l) mm ? i2c communication interface for control, programming and monitoring with pmbus? protocol and psmi protocol ? over temperatu re, output over voltage and overcurrent protection ? 256 bytes of eeprom for user information ? 2 status leds: ok and fail with fault signaling ? high performance servers ? routers ? switches disclaimer: pmbus is a registered trademark of smif, inc .
2 pfe1500 series tech.support@psbel.com product family power level dash v1 output dash width airflow input 3 pfe front - ends 1500 w 12 v 54 mm n: normal 1 r: reverse 2 a: c14 socket ac: c16 socket ah: hvdc socket 1 n normal airflow from output connector to input ac socket ordering pn: pfe1500 - 12 - 054na for c14 ac input connector, input range is 180 vdc ~ 350 vdc and 90 vac ~ 264 vac ordering pn: pfe1500 - 12 - 054nac for c16 ac input connector, i nput range is 180 vdc ~ 350 vdc and 90 vac ~ 264 vac ordering pn: pfe1500 - 12 - 054nah for both ac and hvdc (rf - 203 - d - 1.0) input c onnector, input range is 180 ~ 400 vdc and 90 ~ 264 vac 2 r reverse airflow from input ac socket to output connector ordering pn : pfe1500 - 12 - 054ra for c14 ac input connector, input range is 180 vdc ~ 350 vdc and 90 vac ~ 264 vac ordering pn: pfe1500 - 12 - 054rac for c16 ac input connector, input range is 180 vdc ~ 350 vdc and 90 vac ~ 264 vac ordering pn: pfe1500 - 12 - 054rah for both ac and hvdc (rf - 203 - d - 1.0) input connector, input range is 180 ~ 400 vdc and 90 ~ 264 vac 3 for difference of the ac socket and mechanical outline refer to section 13. s412 product family power level dash v1 output airflow input 5 vsb output pfe front - ends 1500 w 12 v n: normal 4 a: c14 socket ac: c16 socket ah: hvdc socket 12vsb 4 n normal airflow from output connector to input ac socket ordering pn: pfe1500 - 12nas412 for c14 ac input connector, input range is 180 vdc ~ 350 vdc and 90 vac ~ 264 vac ordering pn: pfe1500 - 12nacs412 for c16 ac input connector, input range is 180 vdc ~ 350 vdc and 90 vac ~ 264 vac ordering pn: pfe1500 - 12nahs412 for both ac and hvdc (rf - 203 - d - 1.0) input connector, input ran ge is 180 vdc ~ 400 vdc and 90 vac ~ 264 vac 5 for difference of the ac socket and mechanical outline refer to section 13.
pfe1500 series 3 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae the pfe1500 series ac/dc power supply is combination of analog and dsp control, highly efficient front - end power sup ply. it incorporates resonance - soft - switching technology and interleaved power trains to reduce component stresses, providing increased system reliability and very high efficiency. with a wide input operational voltage range and minimal derating of output power with input voltage and temperature, the pfe1500 power supply maximizes power availability in demanding server, network, and other high availability applications. the supply is fan cooled and ideally suited for integration with a matching airflow path s. the pfc stage is an analogue solution; mcu is used to communicate with dsp chip on secondary side. the dc/dc stage uses soft switching resonant techniques in conjunction with synchronous rectification. an active or - ing device on the output ensures no re verse load current and renders the supply ideally suited for operation in redundant power systems. the always - on standby output , provides power to external power distribution and management controllers. it is protected with an active or - ing device for maxi mum reliability. status information is provided with front - panel leds. in addition, the power supply can be controlled and the fan speed set via the i2c bus. the i2c bus allows full monitoring of the supply, including input and output voltage, current, po wer, and inside temperatures. the fan speed is adjusted automatically depending on the actual power demand and supply temperature and can be overridden through the i2c bus. figure 1 . pfe1500 series block diagr am stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long - term reliability, and cause permanent damage to the supply. vi maxc maximum input continuous 264 vac
4 pfe1500 series tech.support@psbel.com general condition: t a = 0 4 5c unless otherwise specified. v i nom nominal input voltage 100 240 vac 20 0 350 1 vdc v i input volta ge ranges normal operating ( v i min to v i max ) 90 264 vac 180 350 vdc v i red derating input voltage range see figure 7 a and figure 7b 90 180 vac i i max max input current 15 a rms i i p inrush current limitation v i min to v i max , t ntc = 25c ( figure 4 ) 40 a p f i input frequency 47 50/60 64 hz pf power factor v i nom , 50 hz, > 0.3 i 1 nom 0.96 w/va v i on turn - on input voltage 2 ramping up 80 8 4 8 9 vac 1 69 174 1 80 vdc v i off turn - off input voltage ra mping down 75 80 85 vac 16 6 171 17 6 vdc efficiency without fan at ac input v i nom , 0.1 ? i x nom , v x nom , t a = 25c 90 % v i nom , 0.2 ? i x nom , v x nom , t a = 25c 92 v i nom , 0.5 ? i x nom , v x nom , t a = 25c 94 v i nom , i x nom , v x nom , t a = 25c 92 efficiency without fan at dc input v i nom=336 vdc , 0.1 ? i x nom , v x nom , t a = 25c 89 v i nom=336 vdc , 0.2 ? i x nom , v x nom , t a = 25c 9 2 v i nom=336 vdc , 0.5 ? i x nom , v x nom , t a = 25c 9 3.5 v i nom=336 vdc , i x nom , v x nom , t a = 25c 92 t hold hold - up time after last ac zero point to v 1 10.8 v, v sb within regulation, v i = 230 vac , p x nom 10 m s 1 for pfe1500 - 12 - 054nah , pfe1500 - 12 - 054rah an d pfe1500 - 12nahs412, n ormal dc operation input range is 200 vdc to 380 vdc and input range is 180 vdc to 40 0 vd c; input ac range is 90 vac ~ 264 vac. 2 the front - end is provided wit h a minimum hysteresis of 3 v during turn - on and turn - off within the ranges . 4.1 input fuse quick - acting 16 a input fuse (5 x 20 mm) in series the l line inside the power supply protect against severe defects. the fuses are not accessible from the outside and are therefore not serviceable parts. 4.2 inrush current the ac - dc power supply exhibits an x - capacitance of only 3.2 f, resulting in a low and short peak current, when the supply is connected to the mains. the internal bulk capacitor will be charged through a n ntc which will limit the inrush current. note: do not repeat plug - in / out operations within a short time, or else the internal in - rush current limiting device (ntc) may not sufficiently cool down and excessive inrush current or component failure(s) may result.
pfe1500 series 5 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae 4.3 input under - voltage if the sinusoidal input voltage stays below the input under voltage lockout threshold vi on, the supply will be inhibited. once the input voltage returns within the normal operating range, the supply will return to normal operation again. 4.4 power factor correction power factor correction (pfc) is achieved by controlling the input current waveform synchronously with the input voltage. an analog controller is implemented giving outstanding pfc results over a wide input volt age and load ranges. the input current will follow the shape of the input voltage. 4.5 efficiency high efficiency (see figure 2 ) is achieved by using state - of - the - art silicon power devices in conjunction with soft - transition topo logies minimizing switching losses and a full digital control scheme. synchronous rectifiers on the output reduce the losses in the high current output path. the speed of the fan is digitally controlled to keep all components at an optimal operating temper ature regardless of the ambient temperature and load conditions. figure 2 . efficiency vs. load current (ratio metric loading) figure 3 . power factor vs. load current figure 4 . inrush current, vin = 264 vac, 90, ch1: vin (200v/div), ch2: iin (10a/div)
6 pfe1500 series tech.support@psbel.com general condition: t a = 0 4 5c unless otherwise specified. main output v 1 v 1 nom nominal output voltage 0.5 ? i 1 nom , t amb = 25 c 12.0 vdc v 1 set output setpoint accuracy - 0.5 +0.5 % v 1 nom d v 1 tot total regulation v i min to v i max , 0 to 100% i 1 nom , t a min to t a max - 2 +2 % v 1 nom p 1 nom nominal output power 264 vac > v in 180 vac, v 1 = 12 vdc 400 vdc > v in 180 vdc , v 1 = 12 vdc 1500 w refer to figure 7 for derating curve 180 vac > v in 90 vac , v 1 = 12 vdc 1000 w i 1 nom nominal output current 264 vac > v in 180 vac, v 1 = 12 vdc 400 vdc > v in 180 vdc, v 1 = 12 vdc 125 adc refer to figure 7 for derating curve s 180 vac > v in 90 vac , v 1 = 12 vdc 8 3.4 adc v 1 pp output ripple voltage v 1 nom , i 1 nom , 20 mhz bw (see section 5.1) 150 mvpp d v 1 load load regulation v i = v i nom , 0 - 100 % i 1 nom 80 mv d v 1 line line regulation v i =v i min v i max 40 mv d i share current sharing deviation from i 1 tot / n, i 1 > 10% - 3 +3 a d v dyn dynamic load regulation i 1 = 50% i 1 nom , i 1 = 5 100% i 1 nom , d i 1 /d t = 1a/ s - 0.6 0.6 v t rec recovery time i 1 = 50% i 1 nom , i 1 = 5 100% i 1 nom , d i 1 /d t = 1a/ s, recovery within 1% of v 1 nom 1 ms t ac v1 start - up time from ac 2 sec t v1 rise rise time v 1 = 1090% v 1 nom 0.5 10 ms c load capacitive loading t a = 25c 30000 f 3.3/ 5 v sb standby output v sb nom nominal output voltage 0.5 ? i sb nom , t amb = 25c vsb_sel = 1 3.3 vdc v sb set output setpoint accuracy vsb_sel = 0 5.0 vdc vsb_sel = 0 / 1 - 0.5 +0.5 % v 1nom d v sb tot total regulation v i min to v i max , 0 to 100% i sb nom , t a min to t a max - 3 +3 % v sbnom p sb nom nominal output power v sb = 3.3 vdc , 16.5 w v sb = 5.0 vdc, 16.5 i sb nom nominal output current v sb = 3.3 vdc, 5 adc v sb = 5.0 vdc, 3.3 v sb pp output ripple voltage v sb nom , i sb nom , 20 mhz bw (see section 5.1) 100 mvpp d v sb droop 0 - 100 % i sb nom vsb_sel = 1 67 mv vsb_sel = 0 44 i sb max current limitation vsb_sel = 1, 5.25 6 adc vsb_sel = 0, 3.45 4.3 d v sb dyn dynamic load regulation i sb = 50% i sb nom , i sb = 5 100% i sb nom , d i o /d t = 0.5 a/ s, recovery within 1% of v 1 nom - 3 3 % v sbnom t rec recovery time 250 s t ac vsb start - up time from ac v sb = 90% v sb nom 2 sec t vsb rise rise time v sb = 1090% v sb nom 0 .5 30 ms c load capacitive loading t amb = 25c 10000 f
pfe1500 series 7 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae 12 v sb standby output v sb nom nominal output voltage 0.5 ? i sb nom , t amb = 25c 12 vdc v sb set output setpoint accuracy - 1 +1 % v sb nom d v sb tot total regulation v i min to v i max , 0 to 100% i sb nom , t a min to t a max - 3 +3 % v sb nom p sb nom nominal output power v sb = 12 vdc 36 w i sb nom nominal output current v sb = 12 vdc 3 a v sb pp output ripple voltage v sb nom , i sb nom , 20 mhz bw (see section 5.1) 60 120 mvpp d v sb dro op 0 - 100 % i sb nom 270 mv d v sb dyn dynamic load regulation i sb = 50% i sb nom , i sb = 5 100% i sb nom , d i o /d t = 1 a/ s, recovery within 1% of v 1 nom - 0.6 0.6 v t rec recovery time 0.5 ms t ac vsb start - up time from ac v sb = 90% v sb nom 2 s t vsb rise rise time v sb = 1090% v sb nom 20 ms c load capacitive loading t amb = 25c 1,500 f 5.1 output voltage ripple internal capacitance at the 12 v output (behind the or - ing circuitry) is minimized to prevent disturbances during hot plug. in order to provide low output ripple voltage i n the application , external capacitors ( a parallel combination of 10 f tantal um capacitor in parallel with 0.1 f ceramic capacitors ) should be added close to the power supply output. the setup of figure 5 has been used to evalua te suitable capacitor types. the capacitor combinations of table 1 and table 2 should be used to reduce the output ripple voltage. the ripple voltage is measured with 20 mhz bwl, close to the external capacitors. figure 5 . output ripple test setup note: care must be taken when using ceramic capacitors with a total capacitance of 1 f to 50 f on output v1, due to their high quality factor the o utput ripple voltage may be increased in certain frequency ranges due to resonance effects. external capacitor v1 dv1max unit standard test condition: 1 pc 10 f / 63 v electrolytic capacitor 1 pc 0.1 uf / 100 v ceramic capacitor 150 mvpp 1pcs 1000f/ 16v/low esr aluminum/?10x20 120 mvpp 2pcs 47f/16v/x5r/1210 100 mvpp 2pcs 47f/16v/x5r/1210 plus 1pcs 1000f low esr alcap 90 mvpp table 1 . suitable capacitors for v 1 external capacitor vsb dv1max unit standard test condition : 1 p c 10 f / 63 v electrolytic capacitor 1 pc 0.1 uf / 100 v ceramic capacitor 100 mvpp add 1 pc 10f/16 v/x5r/1206 50 mvpp add 2 p cs 10f/1v/x5r/1206 40 mvpp table 2 . suitable capacitors for 3.3v sb and 5v sb the output rip ple voltage on v sb is influenced by the main output v 1 . evaluating v sb output ripple must be done when maximum load is applied to v 1 .
8 pfe1500 series tech.support@psbel.com parameter description / condition min nom max unit f input fuse (l) not user accessible, qui ck - acting (f) 16 a v 1 ov ov threshold v 1 13.3 14.5 vdc t ov v1 ov latch off time v 1 1 ms v sb ov ov threshold v sb 110 120 % v sb t ov vsb ov latch off time v sb 1 ms i v1 lim over current limit ation v 1 v i > 180 vac , t a < 45c v i > 90 vac , t a < 45c 128 93 1 4 0 11 0 a i vsb lim over current limitation v sb t a < 45c for 12 v sb 3.3 3. 6 a t a < 45c for 5 v sb 3.45 4.5 a t a < 45c for 3.3 v sb 5.25 6 .2 a i v1 sc max short circuit current v 1 v 1 < 3 v 20 0 a t v1 sc short circuit regulation time v 1 < 3 v, time until i v1 is limited to < i v1 sc 2 ms t sd over temperature o n heat sinks automatic shut - down 115 1 2 0 c 6.1 overvoltage protection the pfe front - ends provide a fixed threshold overvoltage (ov) protection implemented with a hw compara tor. once an ov condition has been triggered, the supply will shut down and latch the fault condition. the latch can be unlocked by disconnecting the supply from the ac mains or by toggling the pson_l input. 6.2 vsb undervoltage detection both main and stan dby outputs are monitored. 3.3 / 5 v sb led and pwok_h pin signal if the output voltage exceeds 5% of its nominal voltage. output under voltage protection is provided on the standby output only. when v sb falls below 75% of its nominal voltage, the main ou tput v 1 is inhibited. 12 v sb led and pwok_l pin signal if the output voltage exceeds 7% of its nominal voltage. output under voltage protection is provided on both outputs. when either v 1 or v sb falls below 93% of its nominal voltage, the output is inhib ited. 6.3 current limitation 6.3.1 main output when main output runs in current limitation mode its output will turn off below 2 v b ut will retry to recover every 1 s interval. if current limitation mode is still present after the unit retry, output will c ontinuously perform this routine until current is below the current limitation point. the supply will go through soft start every time it retries from current limitation mode. figure 6 . current limitation on v 1 (v i = 230 vac )
pfe1500 series 9 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae t he main output current limitation will decrease if the ambient (inlet) temperature increases beyond 45 c or if the ac input voltage below 180 vac (s ee figure 7 and figure 8 ) for power supply applied in canad a and united states of america and other district respectively ). note that the actual over current protection on v 1 will begin at a current level approximately 5 a higher, see figure 9 . (see als o chapter 9 temperature and fan control for additional information.) figure 7 . iout derating curve s for application in canada and the usa at 45c ambient figure 8 . iout derating curves for app lication in districts other than canada and the usa at 45c ambient figure 9 . ocp derating curve with vinac and ambient temperature for pfe1500 series
10 pfe1500 series tech.support@psbel.com 6.3.2 standby output 3.3 / 5 v sb the standby output exhibits a substant ially rectangular output characteristic down to 0 v (no hiccup mode / latch off). if it runs in current limitation and its output voltage drops below the uv threshold, then the main output will be inhibited (standby re mains on). the current limitation of t he standby output is independent of the ac input voltage. figure 10 . current limitation and temperature derating on 3.3 / 5 v sb 12 v sb on the standby output, a hiccup type over current protection is impleme nted. this protection will shut down the standby output immediately when standby current reaches or exceeds i vsb lim . after an off - time of 1 s the output automatically tries to restart. if the overload condition is removed the output voltage will reach aga in its nominal value. at continuous overload condition the output will repeatedly trying to restart with 1s intervals. a failure on the standby output will shut down both main and stan dby outputs. figure 11 . c urrent limitation o n 12 v sb 0 2 4 6 8 10 12 0 1 2 3 4 5 standby output voltage [v] standby output current [a] 0 1 2 3 4 5 0 2 4 6 8 standby output current [a] standby output voltage [v] vsb=3.3v vsb=5v
pfe1500 series 11 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae parameter description / condition min nom max unit v i mon input rms voltage v i min v i v i max - 2.5 +2.5 % i i mon input rms current i i > 2 a rms - 5 +5 % p i mon true input power i i > 2 a rms - 5 +5 % v 1 mon v 1 voltage - 2 +2 % i 1 mon v 1 current i1 > 25 a - 2 +2 % i1 25 a - 1 +1 a p o nom total output power po > 120 w - 5 +5 % po 120 w - 12 +12 w v sb mon standby voltage 3.3 / 5 v sb models 12 v sb models - 0.2 - 0.5 +0. 2 +0.5 v i sb mon standby current i sb i sb nom 3.3 / 5 v sb models 12 v sb models - 0.5 - 0.5 +0.5 +0.5 a parameter description / condition min nom max unit pskill_h / pson_l / vsb_sel / hotstandbyen_h inputs v il input low level voltage - 0.2 0.8 v v ih input high level voltage 2.4 3.5 v i il, h maximum input sink or source current 0 1 ma r pupskill_h internal pull up resistor on pskill_h 100 k r pupson_l internal pull up resistor on pson_l 10 k r puvsb_sel internal pull up resistor on vsb_sel 10 k r puhotstandbyen_h internal pull up resistor on hotstandbyen_h 10 k r low resistance pin to sgnd for low level 0 1 k r high resistance pin to sgnd for high level 50 k pwok_h output v ol output low level voltage i sink < 4 ma 0 0.4 v v oh output high level voltage i source < 0.5 ma 2.6 3.5 v r pupwok_h internal pull up resistor on pwok_h 1 k acok_h output v ol output low level v oltage i sink < 2 ma 0 0.4 v v oh output high level voltage i source < 50 a 2.6 3.5 v r puacok_h internal pull up resistor on acok_h 10 k smb_alert_l output v ext maximum external pull up voltage 12 v v ol output low level voltage i source < 4 ma 0 0.4 v i oh maximum high level leakage current 10 a r pusmb_alert_l internal pull up resistor on smb_alert_l none k 8.1 electrical cha racteristics
12 pfe1500 series tech.support@psbel.com power supply condition green (ok) led status amber (fail) led status no ac power to all power supplies off off power supply failure (includes over voltage, over current, over temperature and fa n failure) off on power supply warning events where the power supply continues to operate (high temperature, high power and slow fan) off blinking ac present/ 12vsb on (psu off) blinking off power supply on and ok on off table 3 . led status 8.2 interfacing with signals all signal pins have protection diodes implemented to protect internal circuits. when the power supply is not powered, the protection devices start clamping at signal pin voltages exceeding 0.5 v. therefore, all input signals should be driven only by an open collector/drain to prevent back feeding inputs when th e power supply is switched off. if interconn ecting of signal pins of several power supplies is required, then this should be done by decoupling with small signal schottky diodes as shown in examples in ( figure 12 ) except for smb_alert_l, ishare and i 2 c pins . smb_alert_l pin s can be interconnected without decoupling diodes, since these pins have no internal pull up resistor and use a 15 v zener diode as protection device ag ainst positive voltage on pins. ishare pins must be interconnected without any additional components. th is in - /output is disconnected from internal circuits when th e power supply is switched off. figure 12 . interconnection of signal pins 8.3 front leds there will be 2 separate led indicators, one gr een and one amber to indicate the power supply status. there will be a (slow) blinking green power led (ok) to indicate that ac is applied to the psu and the standby voltage is available. this same led shall go steady to indicate that all the power outputs are available. this same led or separate one will blink (slow) or be solid on amber to indicate that the power supply has failed or reached a warning status and therefore a replacement of the unit is/maybe necessary. the led are visible on the power suppl ys exterior face. the led location meets esd requirements. 8.4 present_l this signaling pin is recessed within the connector and will contact only once all other connector contacts are closed. this active - low pin is used to indicate to a power distribution unit controller that a supply is plugged in. t he maximum current on present_l pin should not exceed 10 ma. figure 13 . present_l signal pin p s u 1 p d u p s u 2 v s b _ s e l p s u 1 p d u p s u 2 3 . 3 v v s b _ s e l 3 . 3 v 3 . 3 v p w o k 3 . 3 v p w o k v 1 v s b 0 v p r e s e n t _ l p f e p d u
pfe1500 series 13 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae 8.5 pskill_h input the pskill_h input is active - high and is located on a recessed pin on the connector and is u sed to disconnect the main output as soon as the power supply is being plugged out. this pin should be connected to sgnd in the power distribution unit. the standby output will remain on regardless of the pskill_h input state. 8.6 ac turn - on / drop - outs / ac ok_h the power supply will automatically turn - on when connected to the ac line under the condition that the pson_l signal is pulled low and the ac line is within range. the acok_h signal is active - high. the timing diagram is shown in figure 14 and referenced in table 4 . operating condition min max unit t ac vsb ac line to 90% v vsb 2 sec t ac v1 ac line to 90% v 1 2 sec t acok_h on1 acok_h signal on delay (start - up) 2000 ms t acok_h on2 acok_h signal on delay ( dips) 100 ms t acok_h off acok_h signal off delay 5 ms t vsb v1 del v sb to v 1 delay 10 500 ms t v1 holdup effective v 1 holdup time 10 ms t vsb holdup effective v sb holdup time 20 ms t acok_h v1 acok_h to v 1 holdup 7 ms t acok_h vsb acok_h to v sb holdu p 15 ms t v1 off minimum v 1 off time 1 2 sec t vsb off minimum v sb off time 1 2 sec note: ac short dips means below 10 ms; ac long dips means 10 ms to 100 ms table 4 . ac turn - on / dip timing figure 14 . ac turn - on timing figure 15 . ac short dips figure 16 . ac long dips a c i n p u t v s b v 1 p s o n _ l a c o k _ h p w o k _ h t a c v s b t v s b r i s e t v 1 r i s e t a c v 1 t p w o k _ h d e l t a c o k _ h o n 1 t v s b v 1 d e l a c i n p u t v s b v 1 p s o n _ l a c o k _ h p w o k _ h t v s b h o l d u p t a c o k _ h v s b t a c o k _ h o f f t v 1 h o l d u p t a c o k _ h v 1 t v 1 o f f t v s b o f f t p w o k _ h w a r n
14 pfe1500 series tech.support@psbel.com operating condition min max unit t pson_l v1on pson_l to v 1 delay (on) 2 20 ms t pson_l v1off pson_l to v 1 delay (off) 2 20 ms t pson_l h min pson_l minimum high time 10 ms table 5 . pson_l timing 8.7 pson_l input the pson_l is an internally pulled - up ( 3.3 v) input signal to enable/disable the main output v1 of the front - end. this active - low pin is also used to clear any latched fault condition. the t iming diagram is given in figure 27 and the parameters in table 5 . 8.8 pwok_h signal the pwok_h is an open drain output with an internal pull - up to 3.3 v indicating whether both v sb and v 1 outputs are within regulation. this pin is active - low. the timing diagram is shown in figure 17 and referenced in the table 6 . figure 17 . pson_l and pwok_h turn - on/off timing operating condition min max unit t pwok_h del pwok_h to v 1 delay (on) 100 500 ms t pwok_h warn * pwok_h to v 1 delay (off) caused by: pskill_h 0 1 ms pson_l, ot, fan failure acok_h (time change with loading cond ition) 0.5 0.5 2.5 100 ms ms uv and ov on vsb 1 30 ms oc on v1 (software trigger) - 11 0 ms oc on v1 (ha rdware trigger) - 1 0 ms ov on v1 - 3 0 ms * a positive value means a warning time, a negative value a delay (after fact). table 6 . pwok_h timing 8.9 current share the pfe front - ends have an active current share scheme implemented for v 1 . all the ishare current share pins need to be interconnected in order to activate the sharing function. if a supply has an internal fault or is not turned on, it will disc onnect its ishare pin from the share bus. this will prevent dragging the outp ut down (or up) in such cases. the current share function uses a digital bi - directional data exchange on a recessive bus configuration to transmit and receive current share information. the controller implements a master/slave current share function. the p ower supply providing the largest current among the group is automatically the master. the other supplies will operate as slaves and increase their out put current to a value close to the master by slightly increasing their output voltage. the voltage incre ase is limited to +250 mv. the standby output uses a passive current share method (droop output voltage characteristic). 8.10 sense inputs both main and standby outputs have sense lines implemented to compensate for voltage drop on load wires (no sense line s for 12vsb) . the maximum allowed voltage drop is 200 mv on the positive rail and 100 mv on the pgnd rail. with open sense inputs the main output voltage will rise by 270 mv and the standby output by 50 mv. therefore , if not used, these inputs should be c onnected to the power output and pgnd close to the power supply connector. the sense inputs are protected against short circuit. in this case the power supply will shut down. v s b a c i n p u t v 1 p s o n _ l a c o k _ h p w o k _ h t p s o n _ l v 1 o n t v 1 r i s e t p w o k _ h d e l t p s o n _ l v 1 o f f t p w o k _ h w a r n t p s o n _ l h m i n
pfe1500 series 15 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae 8.11 hot - standby operation the hot - standby operation is an operating mode allowing t o further increase efficiency at light load conditions in a redundant power supply system. under specific conditions one of the power supplies is allowed to disable its dc/dc stage. this will sav e the power losses associated with this power supply and at t he same time the other power supply will operate in a load range having a better efficiency. in order to enable the hot standby operation, the hotstandbyen_h and the ishare pins need to be inter connected. a power supply will only be allowed to enter the h ot - standby mode, when the hotstandbyen_h pin is high, the load current is low (see figure 18 ) and the supply was allowed to enter the hot - standby mode by the system controller via the appropriate i 2 c command (by default disabled). the system controller needs to ensure that only one of the power supplies is allowed to enter the hot - standby mode. if a power supply is in a fault condition, it will pull low its active - high hotstandbyen_h pin which indicates to the other power supply t hat it is not allowed to enter the hot - standby mode or that it needs to return to normal operation should it already have been in the hot - standby mode. note: the system controller needs to ensure that only one of the power supplies is allowed to enter the hot - standby model. figure 19 shows the achievable power loss savings when using the hot - standby mode operation. a total power loss reduction of 5 w is achievable. figure 18 . hot - standby enable/disable current thresholds figure 19 . psu power losses with/without hot - standby mode figure 20 . recommended hot - standby configuration in order to prevent voltage dips when the active power su pply is unplugged while the other is in hot - standby mode, it is strongly recommended to add the external circuit as shown in figure 20 . if the present_l pin status needs also to be read by the system controller, it is recommended to exchange the bipolar transistors with small signal mos transistors or with digital transistors. p s u 1 p s u 2 v s b c s h o t s t a n d b y e n p r e s e n t _ l v s b c s h o t s t a n d b y e n p r e s e n t _ l 3 x 3 k 3
16 pfe1500 series tech.support@psbel.com parameter description / condition min nom max unit v il input low voltage - 0.5 1.0 v v ih input high voltag e 2.3 5.5 v v hys input hysteresis 0.15 v v ol output low voltage 3 ma sink current 0 0.4 v t r rise time for sda and scl 20+0.1cb 3 300 ns t of output fall time vihmin ? vilmax 10 pf < cb 3 < 400 pf 20+0.1cb 3 250 ns i i input current scl/sda 0.1 vd d < vi < 0.9 vdd - 10 10 a c i internal capacitance for each scl/sda 50 pf f scl scl clock frequency 0 100 khz r pu external pull - up resistor f scl 100 khz 1000 ns / cb ? t hdsta hold time (repeated) start f scl 100 khz 4.0 s t low low period of the scl clock f scl 1 00 khz 4.7 s t high high period of the scl clock f scl 100 khz 4.0 s t susta setup time for a repeated start f scl 100 khz 4.7 s t hddat data hold time f scl 100 khz 0 3.45 s t sudat data setup time f scl 100 khz 250 ns t susto setup time for stop condition f scl 100 khz 4.0 s t buf bus free time between stop and start f scl 100 khz 5 ms table 7 . i2c / smbus specification 3 cb = capacitance of bus line in pf, typically in the range of 10400 pf 8.12 i 2 c / smbus communication the interface driver in the pfe supply is referenced to the v1 return. the pfe supply is a communication slave device only; it never initiates messages on the i2c/smbus by itself. the communication bus voltage and timing is defined in table 7 further characterized through: ? there are no internal pull - up resistors ? the sda/scl ios are 3.3/5 v tolerant ? full smbus clock speed of 100 kbps ? clock stretching limited to 1 ms ? scl low time - out of >25 ms with recovery within 10 ms ? recognizes any time start/stop bus conditions figure 21 . physical layer of communication interface the smb_alert_l signal indicates that the power supply is experiencing a problem that the system agent should investigate. this is a logical or of the shutdown and warning events. the power supply responds t o a read command on the general smb_alert_l call address 25(0x19) by sending its status register. communication to the dsp or the eeprom will be possible as long as the input ac voltage is provided. if no ac is present, communication to the unit is possibl e as long as it is connected to a life v1 output (provided e.g. by the redundant unit). if only vsb is provided, communication is not possible. 3 . 3 / 5 v r p u l l - u p t x r x s d a / s c l
pfe1500 series 17 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae figure 22 . i 2 c / smbus timing 4 e12 resistor values, use max 5% resistors, see also figure 22 5 the lsb of the address byte is the r/w bit 8.13 add ress / protocol selectio n (aps) the aps pin provides the possibility to select the address by connecting a resistor to v1 return (0 v). a fixed addressing offset exists between the controller and the eeprom. note: - if the aps pin is left open, t he supply will operate with the p mbus? protocol at controller / eeprom addresses 0xb6 / 0xa6. - the aps pin is only read at start - up of the power supply. therefore, it is not possible to change address dynamically. r aps ( ) 4 protocol i2c address 5 controller eeprom 820 pmbus? 0xb0 0xa0 2700 0xb2 0xa2 5600 0xb4 0xa4 8200 0xb6 0xa6 15000 psmi 0xb0 0xa0 27000 0xb2 0xa2 56000 0xb4 0xa4 180000 0xb6 0xa6 figure 23 . i 2 c address and p rotocol setting 8.14 controler and eeprom access the controller and the eeprom in the power supply share the same i2c bus physical layer (see figure 24 ). an i2c driver device assures logic level shifting (3.3/5 v) and a glitch - free clock stretching. the driver also pulls the sda/scl line to nearly 0 v when driven low by the dsp or the eeprom providing maximum flexibility when additional external bus repeaters are needed. such repeaters usually encode the low state with different volt age levels depending on the transmission direction. the dsp will automatically set the i2c address of the eeprom with the necessary offset when its own address is changed / set. in order to write to the eeprom, first the write protection needs to be disabl ed by sending the appropriate command to the dsp. by default, the write protection is on. the eeprom provides 256 bytes of user memory. none of the bytes are used for the operation of the power supply. figure 24 . i 2 c bus to dps a nd eeprom t r t low t high t low t hdsta t susta t hddat t sudat t susto t buf t of sda scl a d c a p s r a p s 3 . 3 v 1 2 k d s p e e p r o m d r i v e r s d a s c l a p s w p a d d r s c l i s d a i p r o t e c t i o n a d d r e s s & p r o t o c o l s e l e c t i o n
18 pfe1500 series tech.support@psbel.com 8.15 eeprom protocol the eeprom follows the industry communication protocols used for this type of device. even though page write / read commands are defined, it is recommended to use the single byte write / read commands. write the write command fo llows the smbus 1.1 write byte protocol. after the device address with the write bit cleared a first byte with the data address to write to is sent followed by the data byte and the stop condition. a new start condition on the bus should only occur after 5 ms of the last stop condition to allow the eeprom to write the data into its memory. read the read command follows the smbus 1.1 read byte protocol. after the device address with the write bit cleared the data address byte is sent followed by a repeated start, the device address and the read bit set. the eeprom will respond with the data byte at the specified location. 8.16 pmbus? protocol the power management bus ( pmbus? ) is an open standard protocol that defines me ans of communicating with power convers ion and other devices. for more information, please see the system management interface forum web site at www.powersig.org . pmbus? command codes are not register addresses. they describe a specific command to be exec uted. the pfe1500 supply supports the following basic command structures: ? clock stretching limited to 1 ms ? scl low time - out of >25 ms with recovery within 10 ms ? recognized any time start/stop bus conditions write the write protocol is the smbus 1.1 write byte/word protocol. note that the write protocol may end after the command byte or after the first data byte (byte command) or then after sending 2 data bytes (word command). in addition, block write commands are supported with a total maximum length of 255 bytes. see pfe programming manual for further information. read the read protocol is the smbus 1.1 read byte/word protocol. note that the read protocol may request a single byte or word. in addition, block read commands are supported with a total m aximum length of 255 bytes. see pfe programming manual bca.00006 for further information. s a d d r e s s w a d a t a a d d r e s s a d a t a a p d a t a n a p s a d d r e s s w a d a t a a d d r e s s a s a d d r e s s r a s a d d r e s s w a c o m m a n d a d a t a l o w b y t e 1 ) a d a t a h i g h b y t e 1 ) a p 1 ) o p t i o n a l s a d d r e s s w a c o m m a n d a b y t e 1 a b y t e n a p b y t e c o u n t a s a d d r e s s w a c o m m a n d a b y t e 1 a s a d d r e s s r a b y t e n n a p b y t e c o u n t a
pfe1500 series 19 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae 8.17 psmi protocol new power management features in computer systems require the system to communicate with the power supply to access current, voltage, fan speed, and temperature information. current measurements provide data to the system for determining potential system configuration limitations and provide actual system power consumption for facility planning. temperature and fan monitoring allow the system to better manage fan speeds and temperatures for optimizing system acoustics. voltage monitoring allows the system to calculate input wattage and warning of system voltage regulation problems. the power supply management interface (psmi) supports diagnostic capabil ities and allows managing of redundant power supplies. the communication method is smbus. the current design guideline is version 2.12. the communication protocol is register based and defines a read and write communication protocol to read / write to a si ngle register address. all registers are accessed via the same basic command given below. no pec (packet error code) is used. write the write protocol used is the smbus 2.0 write word protocol. all writes are 16 - bit words; byte reads are not supported nor allowed. the shaded areas in the figure indicate bits and bytes written by the psmi master device. see pfe programming manual for further information. read the read protocol used is the smbus 2.0 read word protocol. all reads are 16 - bit words; byte read s are not supported nor allowed. the shaded areas in the figure indicate bits and bytes written by the psmi master device. see pfe programming manual for further information. 8.18 graphical user interface bel power solutions provides with its bel power s olutions i2c utility a windows? xp/vista/win7 compatible graphical user interface allowing the programming and monitoring of the pfe1500 - 12 - 054 front - end. the utility can be downloaded on: belfuse.com/po wer - solutions and supports pmbus? protocols. the gui allows automatic discovery of the units connected to the communication bus and will show them in the navigation tree. in the monitoring view the power supply can be controlled and monitored. if the gui is used in conjunction with the snp - op - board - 01 or ytm.g1q01.0 evaluation kit it is also possible to control the pson_l pin(s) of the power supply. further there is a button to disable the internal fan for approximately 10 seconds. this allows the user to take input power measurements without fan consumptions to check efficiency compliance to the climate saver computing platinum specification. the monitoring screen also allows to enable the hot - standby mode on the power supply. the mode status is monitored and by changing the load current it can be monitored when the power supply is being disabled for further energy savings. this obviously requires 2 power supplies being operated as a redundant system (as in the evaluation kit). note: the user of the gui nee ds to ensure that only one of the power supplies have the hot - standby mode enabled. s a d d r e s s w a r e g i s t e r i d a d a t a l o w b y t e a d a t a h i g h b y t e a p s a d d r e s s w a r e g i s t e r i d a d a t a l o w b y t e a s a d d r e s s r a d a t a h i g h b y t e n a p
20 pfe1500 series tech.support@psbel.com to achieve best cooling results sufficient airflow through the supply must be ensured. do not block or obstruct the airflow at the rear of the supply by placing large objects directly at the output connector. the pfe1500 - 12 - 054na , pfe1500 - 12 - 054nac and pfe1500 - 12 - 054nah are provided with normal airflow, which means t he air enters through the dc - output of the supply and leaves at the ac - inlet. pfe supplies have been designed for horizontal operation. the fan inside of the supply is controlled by a microprocessor. the rpm of the fan is adjusted to ensure optimal supply cooling and is a function of output power and the inlet temperature. for the normal airflow version additional constraints apply because of the ac - connector. in a normal airflow unit, the hot air is exiting the power supply unit at the ac - inlet. the iec c onnector on the unit is rated 105c. if 70c mating connector is used then end user must derated the input power to meet a maximum 70c temperature at the front, see figure 7 in above section. note: it is the responsibility of the user to check the front t emperature in such cases. the unit is not limiting its power automatically to meet such a temperature limitation. figure 26 . airflow direction figure 25 . monitoring dialog of the i2c utility normal airflow normal airflow reverse airflow reverse airflow all rights strictly reserved. reproducti o n or issue to third parties in any form is not permitted without writ ten authorit y from po wer-one. d r a w in g n o . tit l e m a t e ria l fi ni s h di m . i n m m r e visi o n modifie d mech. eng. a pproved elec. e ng. app roved mfg. ap proved a3 >120-4 00: 0. 2 t o l e r a n c e s u n l e s s o t h e r w is e st a t e d : 0.5-30: 0.1 >30-12 0: 0.1 5 s u p e rs e d e s: 5 / 5 www.p ower-o ne.com issued s c a l e s iz e s h e e t wh 2009-0 9-17 wh 2009-1 1-10 - - - - - - snp fa m i ly prod uct g a sn p 1 1 0 0 -1 2 g _ ga 0 0 3 a l l m ate r i a l s used, and fini shed pro d uct, must m eet t h e requir ements of the curr ent r o h s dire cti v e 20 02 / 95 /ec. f or add i t i onal i n f orm at i on u s e oth er data f i l e s , o r a sk .
pfe1500 series 21 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae figure 27 . fan speed vs. main output load esd contact discharge iec / en 61000 - 4 - 2, 8 kv, 25+25 discharges per test point (metallic case, leds, connector body) a esd air discharge iec / en 61000 - 4 - 2, 15 kv, 25+25 discharges per test point (non - metallic user accessible surfaces) a radiated electromagnetic field iec / en 61000 - 4 - 3, 10 v /m, 1 khz/80% amplitude modulation, 1 s pulse modulation, 10 khz2 ghz a burst iec / en 61000 - 4 - 4, level 3 ac port 2 kv, 1 minute dc port 1 kv, 1 minute a surge iec / en 61000 - 4 - 5 line to earth: level 3, 2 kv line to line: level 2, 1 kv a rf conduc ted immunity iec/en 61000 - 4 - 6, level 3, 10 vrms, cw, 0.1 80 mhz a voltage dips and interruptions iec/en 61000 - 4 - 11 1: vi 230 v, 100% load, phase 0 , dip 100%, duration 10 ms 2: vi 230 v, 100% load, phase 0 , dip 100%, duration 20 ms 3: vi 230 v, 10 0% load, phase 0 , dip 100%, duration >20 ms a v sb : a, v 1 : b b 10.1 immunity note: most of the immunity requirements are derived from en 55024:1998/a2:2003.
22 pfe1500 series tech.support@psbel.com conducted emission en55022 / cispr 22: 0.15 30 mhz, qp and avg, single unit class a en55022 / cispr 22: 0.15 30 mhz, qp and a vg, 2 units in rack system class a radiated emission en55022 / cispr 22: 30 mhz 1 ghz, qp, single unit class a en55022 / cispr 22: 30 mhz 1 ghz, qp, 2 units in rack system class a harmonic emissions iec61000 - 3 - 2, vin = 115 vac / 60 hz, & vin = 230 vac / 50 hz, 100% load class a ac flicker iec61000 - 3 - 3, vin = 230 vac / 60 hz, 100% load pass maximum electric strength testing is performed in the factory according to iec/en 60950, and ul 60950. input - to - output electric strength test s should not be repeated in the field. bel power solutions will not honor any warranty claims resulting from electric strength field tests. parameter description / condition min nom max unit agency approvals ul 60950 - 1 second edition can/csa - c22.2 no. 60950 - 1 - 07 second edition iec 60950 - 1:2005 en 60950 - 1:2006 approved by independent body (see ce declaration) isolation strength input (l/n) to case (pe) basic input (l/n) to output reinforced output to case (pe) functional d c creepage / cleara nce primary (l/n) to protective earth (pe) according to safety standard mm primary to secondary electrical strength test input to case according to safety standard k vac input to output output and signals to case parameter description / condition min nom max unit t a ambient temperature v i min to v i max , i 1 nom , i sb nom below 5000 feet altitude 0 +45 c v i min to v i max , i 1 nom , i sb nom below 10,000 feet altitude 0 +40 c t aext extended temp . range derating output +46 +60 c t s storage temperature non - operational - 20 +70 c altitude operational, above sea level, refer derating to ta - 10,000 feet n a audible noise v i nom , 50% i o nom , t a = 25c 60 dba dimensions width 54.5 mm height 40.0 depth 321.5 m weight 1.13 k g 10.2 emission
pfe1500 series 23 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae note: a 3d step file of the power supply casing is available on request. figure 28 side view 1 figure 29 . top view figure 30 . side view 2 figure 31 . front and rear view normal air flow direction
24 pfe1500 series tech.support@psbel.com note: a 3d step file of the power supply casing is available on request. figure 32 . side view 1 figure 33 . top view figure 34 . side view 2 figure 35 . front and rear view normal air flow direction
pfe1500 series 25 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae note: a 3d step file o f the power supply casing is available on request. figure 36 . side view 1 figure 37 . top view figure 38 . side view 2 figure 39 . front and rear view normal air flow direction
26 pfe1500 series tech.support@psbel.com pin name description output 6, 7, 8, 9, 10 v1 +12 vdc main output 1, 2, 3, 4, 5 pgnd po wer ground (return) control pins a1 vsb s tandby positive output (+3.3/5 v sb or 12 v sb ) b1 vsb standby positive output (+3.3/5 v sb or 12 v sb ) c1 vsb standby positive output (+3.3/5 v sb or 12 v sb ) d1 vsb standby positive output (+3.3/5 v sb or 12 v sb ) e 1 vsb standby positive output (+3.3/5 v sb or 12 v sb ) a2 sgnd signal ground (return) b2 sgnd signal ground (return) c2 hotstandbyen_h hot standby enable signal: active - high d2 vsb_sense_r standby output negative sense ( not used for 12 v sb model) e2 vsb _sense standby output positive sense ( not used for 12 v sb model) a3 aps i 2 c address and protocol selection (select by a pull down resistor) b3 n/c reserved c3 sda i 2 c data signal line d3 v1_sense_r main output negative sense e3 v1_sense main output po sitive sense a4 scl i 2 c clock signal line b4 pson_l power supply on input (connect to a2/b2 to turn unit on): active - low c4 smb_alert_l smb alert signal output: active - low d4 n/c reserved e4 acok_h ac input ok signal: active - high a5 pskill_h power su pply kill (lagging pin): active - high b5 ishare current share bus (lagging pin) c5 pwok_h power ok signal output (lagging pin): active - high d5 vsb_sel standby voltage selection (lagging pin) ( not used for 12 v sb model) e5 present_l power supply present (lagging pin): active - low ac input connector: pfe1500 - 12 - 054na/ra: power supplier connector: iec320 c14 type pfe1500 - 12 - 054nac/rac: power supp lier connector: iec320 c16 type pfe1500 - 12 - 054nah/rah: power supplier connector: rongfeng p/n rf - 203 - d - 1.0 mating connector: bizlink, type: bc - 326, http://www.bizlinktech.com/ longw ell, type: ls - 26, http://www.longwell.com/cn/ linetek, type: ls - 24, http://w3.linetek.com.tw/html/f2_e.htm dc output connector: power supply connector: tyco electronics p/n 2 - 1926736 - 3 (note: column 5 is recessed (short pins)) mating connector: tyco electronics p/n 2 - 1926739 - 5 or fci 10108888 - r10253slf
pfe1500 series 27 asia - pacific +86 755 298 85888 europe, middle east +353 61 225 977 north america +1 408 785 5200 ? 201 8 bel power solutions & protection bcd.00733_ae bel power solutions i 2 c utility windows xp/vista/7 compatible gui to program, control and monitor pfe front - ends (and other i 2 c units) n/a bel fuse.com/ power - solutions dual connector board connector board to operate 2 pfe units in parallel. includes an on - board usb to i 2 c converter (use bel power solutions i 2 c utility as desktop software). snp - op - board - 01 or ytm.g1q0 1.0 belfuse.com/power - solutions latch lock optional latch lock to prevent accidental removal of the power supply from the system while the ac plug is engaged. xsl.00019.0 bel power solutions nuclear and medical applications - products are not designed or intended for use as critical components in life support s ystems, equipment used in hazardous environments, or nuclear control systems. technical revisions - the appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. specifications are su bject to change without notice.

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